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d a t a sh eet preliminary speci?cation file under integrated circuits, ic22 1997 jan 06 integrated circuits saa7120; saa7121 digital video encoder (condenc)
1997 jan 06 2 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 features monolithic cmos 3.3 v (5 v) device digital pal/ntsc encoder system pixel frequency 13.5 mhz accepts mpeg decoded data on 8-bit wide input port; input data format cb-y-cr (ccir 656), sav and eav three dacs for y, c and cvbs, two times oversampled with 10 bit resolution real time control of subcarrier cross colour reduction filter closed captioning encoding and wst- and nabts-teletext encoding including sequencer and filter line 23 wide screen signalling encoding fast i 2 c-bus control port (400 khz) encoder can be master or slave programmable horizontal and vertical input synchronization phase programmable horizontal sync output phase internal colour bar generator (cbg) 2 2 bytes in lines 20 (ntsc) for copy guard management system can be loaded via i 2 c-bus down-mode of dacs controlled rise/fall times of synchronization and blanking output signals macrovision pay-per-view copy protection system rev.7 and rev.6.1 as option. this applies to saa7120 only. the device is protected by usa patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. use of the macrovision anti-copy process in the device is licensed for non-commercial home use only. reverse engineering or disassembly is prohibited. please contact your nearest philips semiconductors sales office for more information. qfp44 package. general description the saa7120; saa7121 encodes digital yuv video data to an ntsc or pal cvbs or s-video signal. the circuit accepts ccir compatible yuv data with 720 active pixels per line in 4:2:2 multiplexed formats, for example mpeg decoded data. it includes a sync/clock generator and on-chip dacs. quick reference data symbol parameter min. typ. max. unit v dda analog supply voltage 3.1 3.3 3.5 v v ddd digital supply voltage 3.0 3.3 3.6 v i dda analog supply current -- 62 ma i ddd digital supply current -- 38 ma v i input signal voltage levels ttl compatible v o(p-p) analog output signal voltages y, c, and cvbs without load (peak-to-peak value) 1.2 1.35 1.45 v r l load resistance 75 - 300 w ile lf integral linearity error -- 3 lsb dle lf differential linearity error -- 1 lsb t amb operating ambient temperature 0 - +70 c
1997 jan 06 3 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 ordering information block diagram type number package name description version saa7120; saa7121 qfp44 plastic quad ?at package; 44 leads (lead length 2.35 mm); body 10 10 1.75 mm sot307-2 fig.1 block diagram. handbook, full pagewidth i 2 c-bus interface data manager encoder sync clock output interface d a 40 42 41 21 7 36 8433734 35 4 25, 28, 31 mp7 to mp0 ttx 5, 18, 38 6, 17, 39 1, 20, 22, 23, 26, 29 2 19 3 30 27 24 32, 33 reset sda scl rcv1 rcv2 ttxrq xclk xtalo xtali llc v dda4 v ssa1 v ssa2 sa cvbs y c i 2 c-bus control i 2 c-bus control i 2 c-bus control i 2 c-bus control i 2 c-bus control v ssd1, v ssd2 , v ssd3 v ddd1, v ddd2 , v ddd3 v dda1, v dda2 , v dda3 res. sp rtci ap clock and timing y y c cbcr 44 9 to 16 mbh787 saa7120 saa7121
1997 jan 06 4 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 pinning symbol pin i/o description res. 1 - reserved sp 2 i test pin; connected to digital ground for normal operation ap 3 i test pin; connected to digital ground for normal operation llc 4 i line-locked clock; this is the 27 mhz master clock for the encoder v ssd1 5 i digital ground 1 v ddd1 6 i digital supply voltage 1 rcv1 7 i/o raster control 1 for video port; this pin receives/provides a vs/fs/fseq signal rcv2 8 i/o raster control 2 for video port; this pin provides an hs pulse of programmable length or receives an hs pulse mp7 9 i mpeg port; it is an input for ccir 656 style multiplexed cb y, cr data mp6 10 i mp5 11 i mp4 12 i mp3 13 i mp2 14 i mp1 15 i mp0 16 i v ddd2 17 i digital supply voltage 2 v ssd2 18 i digital ground 2 rtci 19 i real time control input; if the llc clock is provided by an saa7111 or saa7151b, rtci should be connected to pin rtco of the decoder to improve the signal quality res. 20 - reserved sa 21 i the i 2 c-bus slave address select input pin; low: slave address = 88h, high = 8ch res. 22 - reserved res. 23 - reserved c 24 o analog output of the chrominance signal v dda1 25 i analog supply voltage 1 for the c dac res. 26 - reserved y 27 o analog output of vbs signal v dda2 28 i analog supply voltage 2 for the y dac res. 29 - reserved cvbs 30 o analog output of the cvbs signal v dda3 31 i analog supply voltage 3 for the cvbs dac v ssa1 32 i analog ground 1 for the dacs v ssa2 33 i analog ground 2 for the oscillator and reference voltage xtalo 34 o crystal oscillator output (to crystal) xtali 35 i crystal oscillator input (from crystal); if the oscillator is not used, this pin should be connected to ground v dda4 36 i analog supply voltage 4 for the oscillator and reference voltage xclk 37 o clock output of the crystal oscillator
1997 jan 06 5 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 v ssd3 38 i digital ground 3 v ddd3 39 i digital supply voltage 3 reset 40 i reset input, active low; after reset is applied, all digital i/os are in input mode; the i 2 c-bus receiver waits for the start condition scl 41 i i 2 c-bus serial clock input sda 42 i/o i 2 c-bus serial data input/output ttxrq 43 o teletext request output, indicating when bit stream is valid ttx 44 i teletext bit stream input symbol pin i/o description fig.2 pin configuration. handbook, full pagewidth saa7120 saa7121 mbh790 1 res. sp ap llc v ddd1 v ssd1 rcv1 rcv2 mp7 mp6 mp5 mp4 mp3 mp2 mp1 mp0 v ddd2 v ssd2 rtci res. sa res. 2 3 4 5 6 7 8 9 10 11 33 v ssa2 v ssa1 v dda3 v dda2 v dda1 y c cvbs res. res. res. 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 ttx ttxrq sda scl xclk xtali xtalo v ddd3 v dda4 v ssd3 reset 43 42 41 40 39 38 37 36 35 34
1997 jan 06 6 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 functional description the digital video encoder (condenc) encodes digital luminance and colour difference signals simultaneously into analog cvbs and s-video signals. ntsc-m, pal b/g, and sub-standards are supported. both interlaced and non-interlaced operation is possible for all standards. the basic encoder function consists of subcarrier generation, colour modulation and the insertion of synchronization signals. luminance and chrominance signals are filtered in accordance with the standard requirements of rs-170-a and ccir 624 . for ease of analog post-filtering the signals are oversampled twice with respect to the pixel clock prior to digital-to-analog conversion. the filter characteristics are shown in figs 3 and 4. the dacs for y, c, and cvbs have 10-bit resolution. the 8-bit multiplexed cb-y-cr formats are ccir 656 (d1 format) compatible, but the sav and eav codes can be decoded optionally when the device is to operate in slave mode. it is also possible to connect a philips digital video decoder (saa7111 or saa7151b) to the condenc. via pin rtci, connected to rtco of a decoder, information concerning the actual subcarrier, pal-id and (if used in conjunction with the saa7111) the subcarrier phase can be inserted. the condenc synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals. wide screen signalling data can be loaded via the i 2 c-bus. it is inserted into line 23 for 50 hz field rate standards. the ic contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with macrovision. possibilities are provided for setting video parameters: black and blanking level control colour subcarrier frequency variable burst amplitude. handbook, full pagewidth 6 (1) (2) (4) (3) 8101214 6 0 024 mgd672 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) fig.3 luminance transfer characteristic 1. (1) ccrs1 = 0; ccrs0 = 1. (2) ccrs1 = 1; ccrs0 = 0. (3) ccrs1 = 0; ccrs0 = 0. (4) ccrs1 = 1; ccrs0 = 1.
1997 jan 06 7 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 handbook, halfpage 02 (1) 6 1 0 - 1 - 2 - 3 - 4 - 5 mbe736 4 f (mhz) g v (db) (1) ccrs1 = 0; ccrs0 = 0. fig.4 luminance transfer characteristic 2. during reset ( reset = low) and after reset is released, all digital i/o stages are set to input mode. a reset forces the i 2 c-bus interface to abort a running bus transfer and sets register 3a to 03h, register 61 to 06h, registers 6bh and 6eh to 00h and bit ttx60 to 0. all other control registers are not influenced by a reset. encoder v ideo path the encoder generates out of y, u and v baseband signals luminance and colour subcarrier output signals, suitable for use as cvbs or separate y and c signals. luminance is modified in gain and in offset (the latter programmable in a certain range to enable different black level set-ups). a fixed synchronization level in accordance with standard composite synchronization schemes is inserted. the inserted blanking level is programmable to allow for manipulations with macrovision anti-taping. additional insertion of agc super-white pulses, programmable in height, is supported. handbook, full pagewidth 6 8 10 12 14 6 0 024 mbe737 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) (1) (2) (1) scbw = 1. (2) scbw = 0. fig.5 chrominance transfer characteristic 1.
1997 jan 06 8 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 in order to enable easy analog post-filtering, luminance is interpolated from 13.5 mhz data rate to 27 mhz data rate, providing luminance in 10-bit resolution. this filter is also used to define smoothed transients for synchronization pulses and blanking period. for transfer characteristic of the luminance interpolation filter see figs 3 and 4. chrominance is modified in gain (programmable separately for u and v), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 mhz data rate to 27 mhz data rate. one of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for y and c output. for transfer characteristics of the chrominance interpolation filter see figs 5 and 6. the amplitude, beginning and ending of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. the numeric ratio between y and c outputs is in accordance with set standards. t eletext insertion and encoding pin ttx receives a wst- or nabts-teletext bitstream sampled at the llc clock. at each rising edge of output (1) scbw = 1. (2) scbw = 0. handbook, halfpage 0 0.4 0.8 1.6 2 0 - 4 - 6 - 2 mbe735 1.2 f (mhz) g v (db) (1) (2) fig.6 chrominance transfer characteristic 2. signal ttxrq a single teletext bit has to be provided after a programmable delay at input pin. phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. ttxrq provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines selectable independently for both fields. the internal insertion window for text is set to 360 (pal-wst), 296 (ntsc-wst) or 288 (nabts) teletext bits including clock run-in bits. for protocol and timing see fig.7. c losed caption encoder using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. the actual line number where data is to be encoded in, can be modified in a certain range. data clock frequency is in accordance with definition for ntsc-m standard 32 times horizontal line frequency. data low at the output of the dacs corresponds to 0 ire, data high at the output of the dacs corresponds to approximately 50 ire. it is also possible to encode closed caption data for 50 hz field frequencies at 32 times horizontal line frequency. a nti - taping (saa7120 only ) for more information contact your nearest philips semiconductors sales office. data manager in the data manager, real time arbitration on the data stream to be encoded is performed. a pre-defined colour look-up table located in this block can be read out in a pre-defined sequence (8 steps per active video line), achieving a colour bar test pattern generator without the need for an external data source. the colour bar function is under software control only. output interface/dacs in the output interface encoded y and c signals are converted from digital to analog in 10-bit resolution.
1997 jan 06 9 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 y and c signals are also combined to a 10-bit cvbs signal. the cvbs output occurs with the same processing delay as the y and c outputs. absolute amplitude at the input of the dac for cvbs is reduced by 15 16 with respect to y and c dacs to make maximum use of conversion ranges. outputs of the dacs can be set together in two groups via software control to minimum output voltage for either purpose. synchronization synchronization of the condenc is able to operate in two modes; slave mode and master mode. in the slave mode, the circuit accepts synchronization pulses at the bidirectional rcv1 port. the timing and trigger behaviour related to rcv1 can be influenced by programming the polarity and the on-chip delay of rcv1. active slope of rcv1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. if the horizontal phase is not to be influenced by rcv1, a horizontal synchronization pulse needs to be supplied at the pin rcv2. timing and trigger behaviour can also be influenced by rcv2. if there are missing pulses at rcv1 and/or rcv2, the time base of condenc runs free, thus an arbitrary number of synchronization slopes may be absent, but no additional pulses (with the incorrect phase) must occur. if the vertical and horizontal phase is derived from rcv1, rcv2 can be used for horizontal or composite blanking input or output. alternatively, the device can be triggered by auxiliary codes in a ccir 656 data stream at the mp port. in the master mode, the time base of the circuit continuously runs free. on the rcv1 port, the device can output: a vertical synchronisation signal (vs) with 3 or 2.5 lines duration, or an odd/even signal which is low in odd fields, or a field sequence signal (fseq) which is high in the first of 4 or 8 fields respectively. on the rcv2 port, the device can provide a horizontal synchronization pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. the polarity of both rcv1 and rcv2 is selectable by software control. the length of a field and the start and end of its active part can be programmed. the active part of a field always starts at the beginning of a line. teletext timing the teletext timing is shown in fig.7. t fd is the time needed to interpolate input data ttx and inserting it into the cvbs and y output signal, such that it appears at t ttx = 10.2 m s (pal) or t ttx = 10.5 m s (ntsc) after the leading edge of the horizontal synchronization pulse. time t pd is the pipeline delay time introduced by the source that is gated by ttxrq in order to deliver ttx data. this delay is programmable by register ttxhd. for every active high-state at output pin ttxrq, a new teletext bit must be provided by the source. since the beginning of the pulses representing the ttxrq signal and the delay between the rising edge of ttxrq and valid teletext input data are fully programmable (ttxhs and ttxhd), the ttx data is always inserted at the correct position after the leading edge of outgoing horizontal synchronization pulse. time t ttxwin is the internally used insertion window for ttx data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 mbits/s (pal), 296 teletext bits at a text data rate of 5.7272 mbits/s (world standard ttx) or 288 teletext bits at a text data rate of 5.7272 mbits/s (nabts). the insertion window is not opened if the control bit ttxen is logic 0. using appropriate programming, all suitable lines of the odd field (ttxovs and ttxove) plus all suitable lines of the even field (ttxevs and ttxeve) can be used for teletext insertion.
1997 jan 06 10 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 fig.7 teletext timing. handbook, full pagewidth t ttxwin t ttx t pd t fd cvbs/y ttx ttxrq textbit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mbh788 analog output voltages the analog output voltages are dependent on the open-loop voltage of the operational amplifiers for full-scale conversion (typical value 1.35 v), the internal series resistor (typical value 2 w ), the external series resistor and the external load impedance. the digital output signals in front of the dacs under nominal conditions occupy different conversion ranges, as indicated in table 1 for a 100 100 colour bar signal. values for the external series resistors result in a 75 w load. input levels and formats the condenc expects digital y, cb, cr data with levels (digital codes) in accordance with ccir 601 (see tables 2 and 3). for c and cvbs outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 ire set-up or without set-up. reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. table 1 digital output signals conversion range table 2 ccir 601 signal component levels conversion range (peak-to-peak) (digits) cvbs, sync tip-to-peak carrier y (vbs) sync tip-to-white 1016 881 colour signals ycbcr white 235 128 128 yellow 210 16 146 cyan 170 166 16 green 145 54 34 magenta 106 202 222 red 81 90 240 blue 41 240 110 black 16 128 128
1997 jan 06 11 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 i 2 c-bus interface the i 2 c-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. it uses 8-bit subaddressing with an auto-increment function. all registers are write only, except one readable status byte. two i 2 c-bus slave addresses are present: 88h: low at pin sa 8ch: high at pin sa. tables 5 and 4 summarize the format of the i 2 c-bus addressing. for more information on how to use the i 2 c-bus see the i 2 c-bus and how to use it , order no. 9398 393 40011. tables 7 to 42 contain the programming information for the subaddresses. table 6 summarises this information. table 3 8-bit multiplexed format (similar to ccir 601 ) table 4 i 2 c-bus address format; see table 5 table 5 explanation of table 4 notes 1. x is the read/write control bit; write: x = logic 0; read: x = logic 1, no subaddressing with read. 2. if more than 1 byte data is transmitted, then auto-increment of the subaddress is performed. bits 0 122 4 567 sample cb 0 y 0 cr 0 y 1 cb 2 y 2 cr 2 y 3 luminance pixel number 0 1 2 3 colour pixel number 0 2 s slave address ack subaddress ack data 0 ack -------- data n ack p part description s start condition slave address 1000100x or 1000110x (1) ack acknowledge, generated by the slave subaddress (2) subaddress byte data data byte -------- continued data bytes and acks p stop condition
1997 jan 06 12 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 table 6 slave receiver (slave address 88h or 8ch) register function sub address data bits (1) d7 d6 d5 d4 d3 d2 d1 d0 null 00 00000000 null 25 00000000 wide screen signal 26 wss7 wss6 wss5 wss4 wss3 wss2 wss1 wss0 wide screen signal 27 wsson 0 wss13 wss12 wss11 wss10 wss9 wss8 real time control, burst start 28 deccol decfis bs5 bs4 bs3 bs2 bs1 bs0 burst end 29 0 0 be5 be4 be3 be2 be1 be0 copy guard odd 0 2a cgo07 cgo06 cgo05 cgo04 cgo03 cgo02 cgo01 cgo00 copy guard odd 1 2b cgo17 cgo16 cgo15 cgo14 cgo13 cgo12 cgo11 cgo10 copy guard even 0 2c cge07 cge06 cge05 cge04 cge03 cge02 cge01 cge00 copy guard even 1 2d cge17 cge16 cge15 cge14 cge13 cge12 cge11 cge10 copy guard enable 2e cgen1 cgen0 0 0 0 0 0 0 null 2f 00000000 null 39 00000000 input port control 3a cbenb 0 0 symp 0 0 y2c uv2c chrominance phase 5a chps7 chps6 chps5 chps4 chps3 chps2 chps1 chps0 gain u 5b gainu7 gainu6 gainu5 gainu4 gainu3 gainu2 gainu1 gainu0 gain v 5c gainv7 gainv6 gainv5 gainv4 gainv3 gainv2 gainv1 gainv0 gain u msb, real time control, black level 5d gainu8 decoe blckl5 blckl4 blckl3 blckl2 blckl1 blckl0 gain v msb, real time control, blanking level 5e gainv8 decph blnnl5 blnnl4 blnnl3 blnnl2 blnnl1 blnnl0 ccr, blanking level vbi 5f ccrs1 ccrs0 blnvb5 blnvb4 blnvb3 blnvb2 blnvb1 blnvb0 null 60 00000000 standard control 61 0 down inpi ygs 0 scbw pal fise rtc enable, burst amplitude 62 rtce bsta6 bsta5 bsta4 bsta3 bsta2 bsta1 bsta0 subcarrier 0 63 fsc07 fsc06 fsc05 fsc04 fsc03 fsc02 fsc01 fsc00 subcarrier 1 64 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc09 fsc08 subcarrier 2 65 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16
1997 jan 06 13 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 note 1. all bits labelled 0 are reserved. they must be programmed with logic 0. subcarrier 3 66 fsc31 fsc30 fsc29 fsc28 fsc27 fsc26 fsc25 fsc24 line 21 odd 0 67 l21o07 l21o06 l21o05 l21o04 l21o03 l21o02 l21o01 l21o00 line 21 odd 1 68 l21o17 l21o16 l21o15 l21o14 l21o13 l21o12 l21o11 l21o10 line 21 even 0 69 l21e07 l21e06 l21e05 l21e04 l21e03 l21e02 l21e01 l21e00 line 21 even 1 6a l21e17 l21e16 l21e15 l21e14 l21e13 l21e12 l21e11 l21e10 rcv port control 6b srcv11 srcv10 trcv2 orcv1 prcv1 cblf orcv2 prcv2 trigger control 6c htrig7 htrig6 htrig5 htrig4 htrig3 htrig2 htrig1 htrig0 trigger control 6d htrig10 htrig9 htrig8 vtrig4 vtrig3 vtrig2 vtrig1 vtrig0 multi control 6e sblbn 0 phres1 phres0 0 0 flc1 flco closed caption, teletext enable 6f ccen1 ccen0 ttxen sccln4 sccln3 sccln2 sccln1 sccln0 rcv2 output start 70 rcv2s7 rcv2s6 rcv2s5 rcv2s4 rcv2s3 rcv2s2 rcv2s1 rcv2s0 rcv2 output end 71 rcv2e7 rcv2e6 rcv2e5 rcv2e4 rcv2e3 rcv2e2 rcv2e1 rcv2e0 msbs rcv2 output 72 0 rcv2e10 rcv2e9 rcv2e8 0 rcv2s10 rcv2s9 rcv2s8 ttx request h start 73 ttxhs7 ttxhs6 ttxhs5 ttxhs4 ttxhs3 ttxhs2 ttxhs1 ttxhs0 ttx request h delay 74 ttxhd7 ttxhd6 ttxhd5 ttxhd4 ttxhd3 ttxhd2 ttxhd1 ttxhd0 v-sync shift 75 0 0 0 0 0 vs_s2 vs_s1 vs_s0 ttx odd request v s 76 ttxovs7 ttxovs6 ttxovs5 ttxovs4 ttxovs3 ttxovs2 ttxovs1 ttxovs0 ttx odd request v e 77 ttxove7 ttxove6 ttxove5 ttxove4 ttxove3 ttxove2 ttxove1 ttxove0 ttx even request v s 78 ttxevs7 ttxevs6 ttxevs5 ttxevs4 ttxevs3 ttxevs2 ttxevs1 ttxevs0 ttx even request v e 79 ttxeve7 ttxeve6 ttxeve5 ttxeve4 ttxeve3 ttxeve2 ttxeve1 ttxeve0 first active line 7a fal7 fal6 fal5 fal4 fal3 fal2 fal1 fal0 last active line 7b lal7 lal6 lal5 lal4 lal3 lal2 lal1 lal0 msb vertical 7c ttx60 lal8 0 fal8 ttxeve8 ttxove8 ttxevs8 ttxovs8 null 7d 0 0 0 00000 disable ttx line 7e line12 line11 line10 line9 line8 line7 line6 line5 disable ttx line 7f line20 line19 line18 line17 line16 line15 line14 line13 register function sub address data bits (1) d7 d6 d5 d4 d3 d2 d1 d0
1997 jan 06 14 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 slave receiver table 7 subaddress 26 and 27 table 8 subaddress 28 and 29 table 9 subaddress 2a to 2d table 10 subaddress 2e data byte logic level description wss - wide screen signalling bits: 13 to 11 = reserved 10 to 8 = subtitles 7 to 4 = enhanced services 3 to 0 = aspect ratio wsson 0 wide screen signalling output is disabled 1 wide screen signalling output is enabled data byte logic level description remarks bs - starting point of burst in clock cycles pal : bs = 33 (21h) ntsc : bs = 25 (19h) be - ending point of burst in clock cycles pal : bs = 29 (1dh) ntsc : bs = 29 (1dh) deccol 0 disable colour detection bit of rtci input 1 enable colour detection bit of rtci input bit rtce must be set to 1 (see fig.10) decfis 0 ?eld sequence as fise in subaddress 61 1 ?eld sequence as fise bit in rtci input bit rtce must be set to 1 (see fig.10) data byte description remarks cgo0 ?rst byte of copy guard data, odd ?eld lsbs of the respective bytes are encoded immediately after run-in and framing code, the msbs of the respective bytes have to carry the parity bit, in accordance with the de?nition of line 20 encoding format. cgo1 second byte of copy guard data, odd ?eld cge0 ?rst byte of copy guard data, even ?eld cge1 second byte of copy guard data, even ?eld data byte description ccen1 ccen0 0 0 copy guard encoding off 0 1 enables encoding in ?eld 1 (odd) 1 0 enables encoding in ?eld 2 (even) 1 1 enables encoding in both ?elds
1997 jan 06 15 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 table 11 subaddress 3a table 12 subaddress 5a remark : in subaddresses 5b, 5c, 5d, 5e and 62 all ire values are rounded up. table 13 subaddress 5b and 5d table 14 subaddress 5c and 5e data byte logic level description uv2c 0 cb, cr data are twos complement 1 cb, cr data are straight binary; default after reset y2c 0 y data is twos complement 1 y data is straight binary; default after reset symp 0 horizontal and vertical trigger is taken from rcv2 and rcv1 respectively; default after reset 1 horizontal and vertical trigger is decoded out of ccir 656 compatible data at mp port cbenb 0 data from input ports is encoded; default after reset 1 colour bar with ?xed colours is encoded data byte description value result chps phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees 3fh pal-b/g and data from input ports 69h pal-b/g and data from look-up table 67h ntsc-m and data from input ports 89h ntsc-m and data from look-up table data byte description conditions remarks gainu variable gain for cb signal; input representation accordance with ccir 601 white-to-black = 92.5 ire gainu = - 2.17 nominal to +2.16 nominal gainu = 0 output subcarrier of u contribution = 0 gainu = 118 (76h) output subcarrier of u contribution = nominal white-to-black = 100 ire gainu = - 2.05 nominal to +2.04 nominal gainu = 0 output subcarrier of u contribution = 0 gainu = 125 (7dh) output subcarrier of u contribution = nominal data byte description conditions remarks gainv variable gain for cr signal; input representation accordance with ccir 601 white-to-black = 92.5 ire gainv = - 1.55 nominal to +1.55 nominal gainv = 0 output subcarrier of v contribution = 0 gainv = 165 (a5h) output subcarrier of v contribution = nominal white-to-black = 100 ire gainv = - 1.46 nominal to +1.46 nominal gainv = 0 output subcarrier of v contribution = 0 gainv = 175 (afh) output subcarrier of v contribution = nominal
1997 jan 06 16 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 table 15 subaddress 5d notes 1. output black level/ire = blckl 2/6.29 + 34.0 2. output black level/ire = blckl 2/6.18 + 31.7 table 16 subaddress 5e notes 1. output black level/ire = blnnl 2/6.29 + 25.4 2. output black level/ire = blnnl 2/6.18 + 25.9 table 17 subaddress 5f table 18 logic levels and function of ccrs data byte description conditions remarks blckl variable black level; input representation accordance with ccir 601 white-to-sync = 140 ire (1) recommended value: blckl = 42 (2ah) blckl = 0 output black level = 34 ire blckl = 63 (3fh) output black level = 54 ire white-to-sync = 143 ire (2) recommended value: blckl = 35 (23h) blckl = 0 output black level = 32 ire blckl = 63 (3fh) output black level = 52 ire decoe real time control logic 0 disable odd/even ?eld control bit from rtci logic 1 enable odd/even ?eld control bit from rtci (see fig.10) data byte description conditions remarks blnnl variable blanking level white-to-sync = 140 ire (1) recommended value: blnnl = 46 (2eh) blnnl = 0 output blanking level = 25 ire blnnl = 63 (3fh) output blanking level = 45 ire white-to-sync = 143 ire (2) recommended value: blnnl = 53 (35h) blnnl = 0 output blanking level = 26 ire blnnl = 63 (3fh) output blanking level = 46 ire decph real time control logic 0 disable subcarrier phase reset bit from rtci logic 1 enable subcarrier phase reset bit from rtci (see fig.10) data byte description blnvb variable blanking level during vertical blanking interval is typically identical to value of blnnl ccrs select cross colour reduction ?lter in luminance; see table 18 ccrs1 ccrs0 description 0 0 no cross colour reduction; for overall transfer characteristic of luminance see fig.3 0 1 cross colour reduction #1 active; for overall transfer characteristic see fig.3 1 0 cross colour reduction #2 active; for overall transfer characteristic see fig.3 1 1 cross colour reduction #3 active; for overall transfer characteristic see fig.3
1997 jan 06 17 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 table 19 subaddress 61 table 20 subaddress 62h table 21 subaddress 62h data byte logic level description fise 0 864 total pixel clocks per line; default after reset 1 858 total pixel clocks per line pal 0 ntsc encoding (non-alternating v component) 1 pal encoding (alternating v component); default after reset scbw 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 3 and 4) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 3 and 4); default after reset ygs 0 luminance gain for white - black 100 ire; default after reset 1 luminance gain for white - black 92.5 ire including 7.5 ire set-up of black inpi 0 pal switch phase is nominal; default after reset 1 pal switch phase is inverted compared to nominal down 0 dacs for cvbs, y and c in normal operational mode; default after reset 1 dacs for cvbs, y and c forced to lowest output voltage data byte logic level description rtce 0 no real time control of generated subcarrier frequency 1 real time control of generated subcarrier frequency through saa7151b or saa7111 (timing see fig.10) data byte description conditions remarks bsta amplitude of colour burst; input representation in accordance with ccir 601 white-to-black = 92.5 ire; burst = 40 ire; ntsc encoding recommended value: bsta = 63 (3fh) bsta = 0 to 2.02 nominal white-to-black = 92.5 ire; burst = 40 ire; pal encoding recommended value: bsta = 45 (2dh) bsta = 0 to 2.82 nominal white-to-black = 100 ire; burst = 43 ire; ntsc encoding recommended value: bsta = 67 (43h) bsta = 0 to 1.90 nominal white-to-black = 100 ire; burst = 43 ire; pal encoding recommended value: bsta = 47 (2fh) bsta = 0 to 3.02 nominal
1997 jan 06 18 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 table 22 subaddress 63 to 66 (four bytes to program subcarrier frequency) note 1. examples: a) ntsc-m: f fsc = 227.5, f llc = 1716 ? fsc = 569408543 (21f07c1fh). b) pal-b/g: f fsc = 283.7516, f llc = 1728 ? fsc = 705268427 (2a098acbh). table 23 subaddress 67 to 6a table 24 subaddress 6b data byte description conditions remarks fsc0 to fsc3 f fsc = subcarrier frequency (in multiples of line frequency); f llc = clock frequency (in multiples of line frequency) , rounded up; see note 1 fsc3 = most signi?cant byte fsc0 = least signi?cant byte data byte description remarks l21o0 ?rst byte of captioning data, odd ?eld lsbs of the respective bytes are encoded immediately after run-in and framing code, the msbs of the respective bytes have to carry the parity bit, in accordance with the de?nition of line 21 encoding format. l21o1 second byte of captioning data, odd ?eld l21e0 ?rst byte of extended data, even ?eld l21e1 second byte of extended data, even ?eld data byte logic level description prcv2 0 polarity of rcv2 as output is active high, rising edge is taken when input, respectively; default after reset 1 polarity of rcv2 as output is active low, falling edge is taken when input, respectively orcv2 0 pin rcv2 is switched to input; default after reset 1 pin rcv2 is switched to output cblf 0 if orcv2 = high, pin rcv2 provides an href signal (horizontal reference pulse that is de?ned by rcv2s and rcv2e, also during vertical blanking interval); default after reset if orcv2 = low and bit symp = low, signal input to rcv2 is used for horizontal synchronization only (if trcv2 = 1); default after reset 1 if orcv2 = high, pin rcv2 provides a composite-blanking-not signal, for example a reference pulse that is de?ned by rcv2s and rcv2e, excluding vertical blanking interval, which is de?ned by fal and lal if orcv2 = low and bit symp = low, signal input to rcv2 is used for horizontal synchronization (if trcv2 = 1) and as an internal blanking signal prcv1 0 polarity of rcv1 as output is active high, rising edge is taken when input; default after reset 1 polarity of rcv1 as output is active low, falling edge is taken when input orcv1 0 pin rcv1 is switched to input; default after reset 1 pin rcv1 is switched to output trcv2 0 horizontal synchronization is taken from rcv1 port (at bit symp = low) or from decoded frame sync of ccir 656 input (at bit symp = high); default after reset 1 horizontal synchronization is taken from rcv2 port (at bit symp = low) srcv1 - de?nes signal type on pin rcv1; see table 25 fsc f fsc f llc ------- - 2 32 ? ? ?? =
1997 jan 06 19 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 table 25 logic levels and function of srcv1 table 26 subaddress 6c and 6d table 27 subaddress 6d table 28 subaddress 6e table 29 logic levels and function of phres data byte as output as input function srcv11 srcv10 0 0 vs vs vertical sync each ?eld; default after reset 0 1 fs fs frame sync (odd/even) 1 0 fseq fseq ?eld sequence, vertical sync every fourth ?eld (pal = 0) or eighth ?eld (pal = 1) 1 1 not applicable not applicable - data byte description htrig sets the horizontal trigger phase related to signal on rcv1 or rcv2 input values above 1715 (fise = 1) or [1727 (fise = 0)] are not allowed increasing htrig decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of rcv used for triggering at htrig = 398h [398h] data byte description vtrig sets the vertical trigger phase related to signal on rcv1 input increasing vtrig decreases delays of all internally generated timing signals, measured in half lines variation range of vtrig = 0 to 31 (1fh) data byte logic level description sblbn 0 vertical blanking is de?ned by programming of fal and lal; default after reset 1 vertical blanking is forced in accordance with ccir 624 (50 hz) or rs170a (60 hz) phres - selects the phase reset mode of the colour subcarrier generator; see table 29 flc - ?eld length control; see table 30 data byte description phres1 phres0 0 0 no reset or reset via rtci from saa7111 if bit rtce = 1; default after reset 0 1 reset every two lines 1 0 reset every eight ?elds 1 1 reset every four ?elds
1997 jan 06 20 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 table 30 logic levels and function of flc table 31 subaddress 6f table 32 logic levels and function of ccen table 33 subaddress 70 to 72 data byte description flc1 flc0 0 0 interlaced 312.5 lines/?eld at 50 hz, 262.5 lines/?eld at 60 hz; default after reset 0 1 non-interlaced 312 lines/?eld at 50 hz, 262 lines/?eld at 60 hz 1 0 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz 1 1 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz data byte logic level description ccen - enables individual line 21 encoding; see table 32 ttxen 0 disables teletext insertion 1 enables teletext insertion sccln - selects the actual line, where closed caption or extended data are encoded line = (sccln + 4) for m-systems line = (sccln + 1) for other systems data byte description ccen1 ccen0 0 0 line 21 encoding off 0 1 enables encoding in ?eld 1 (odd) 1 0 enables encoding in ?eld 2 (even) 1 1 enables encoding in both ?elds data byte description rcv2s start of output signal on pin rcv2 values above 1715 (fise = 1) or [1727 (fise = 0)] are not allowed ?rst active pixel at analog outputs (corresponding input pixel coinciding with rcv2) at rcv2s = 11ah [0fdh] rcv2e end of output signal on pin rcv2 values above 1715 (fise = 1) or [1727 (fise = 0)] are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with rcv2) at rcv2e = 694h [687h]
1997 jan 06 21 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 table 34 subaddress 73 and 74 table 35 subaddress 75 table 36 subaddress 76, 77 and 7c table 37 subaddress 78, 79 and 7c table 38 subaddress 7c table 39 subaddress 7a to 7c data byte description ttxhs start of signal on pin ttxrq see fig.7 ttxhd indicates the delay in clock cycles between rising edge of ttxrq output and valid data on pin ttx minimum value has to be ttxhd = 2 data byte description vs_s vertical sync. shift between rcv1 and rcv2 (switched to output) in master mode it is possible to shift h-sync (rcv2; cblf = 0) against v-sync (rcv1; srcv1 = 00) standard value: vs_s = 3 data byte description ttxovs ?rst line of occurrence of signal on pin ttxrq in odd ?eld line = (ttxovs + 4) for m-systems line = (ttxovs + 1) for other systems ttxove last line of occurrence of signal on pin ttxrq in odd ?eld line = (ttxove + 3) for m-systems line = ttxove for other systems data byte description ttxevs ?rst line of occurrence of signal on pin ttxrq in even ?eld line = (ttxevs + 4) for m-systems line = (ttxevs + 1) for other systems ttxeve last line of occurrence of signal on pin ttxrq in even ?eld line = (ttxeve + 3) for m-systems line = ttxeve for other systems data byte logic level description ttx60 0 enables nabts (fise = 1) or european ttx (fise = 0); default after reset 1 enables world standard teletext 60 hz (fise = 1) data byte description fal ?rst active line = fal + 4 for m-systems, = fal + 1 for other systems, measured in lines fal = 0 coincides with the ?rst ?eld synchronization pulse lal last active line = lal + 3 for m-systems, = lal for other system, measured in lines lal = 0 coincides with the ?rst ?eld synchronization pulse
1997 jan 06 22 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 table 40 subaddress 7e and 7f slave transmitter table 41 slave transmitter (slave address 89h or 8dh) table 42 no subaddress data byte description line individual lines in both ?elds (pal counting) can be disabled for insertion of teletext by the respective bits, disabled line = linexx (50 hz ?eld rate) this bit mask is effective only, if the lines are enabled by ttxovs/ttxove and ttxevs/ttxeve register function subaddress data byte d7 d6 d5 d4 d3 d2 d1 d0 status byte - ver2 ver1 ver0 ccrdo ccrde 0 fseq o_e data byte logic level description ver - version identi?cation of the device. it will be changed with all versions of the device that have different programming models. current version is 000 binary. ccrdo 1 closed caption bytes of the odd ?eld have been encoded. 0 the bit is reset after information has been written to the subaddresses 67 and 68. it is set immediately after the data has been encoded. ccrde 1 closed caption bytes of the even ?eld have been encoded. 0 the bit is reset after information has been written to the subaddresses 69 and 6a. it is set immediately after the data has been encoded. fseq 1 during ?rst ?eld of a sequence (repetition rate: ntsc = 4 ?elds, pa l = 8 ?elds). 0 not ?rst ?eld of a sequence. o_e 1 during even ?eld. 0 during odd ?eld.
1997 jan 06 23 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 characteristics v ddd = 3.0 to 3.6 v; t amb = 0 to +70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit supply v dda analog supply voltage 3.1 3.5 v v ddd digital supply voltage 3.0 3.6 v i dda analog supply current note 1 - 62 ma i ddd digital supply current note 1 - 38 ma inputs v il low level input voltage (except sda, scl, ap, sp and xtali) - 0.5 +0.8 v v ih high level input voltage (except, sda, scl, ap, sp and xtali) 2.0 v ddd + 0.3 v i li input leakage current - 1 m a c i input capacitance clocks - 10 pf data - 8pf i/os at high impedance - 8pf outputs v ol low level output voltage (except sda and xtalo) i ol =4ma - 0.4 v v oh high level output voltage (except, sda, and xtalo) i oh =4ma v ddd - 4 - v i 2 c-bus; sda and scl v il low level input voltage - 0.5 v ddd + 0.3 v v ih high level input voltage 2.3 v ddd + 0.3 v i i input current v i = low or high - 10 +10 m a v ol low level output voltage (sda) i ol =3ma - 0.4 v i o output current during acknowledge 3 - ma clock timing (llc) t llc cycle time note 2 34 41 ns d duty factor t high /t llc note 3 40 60 % t r rise time note 2 - 5ns t f fall time note 2 - 6ns input timing t su;dat input data set-up time (any pin except scl, sda, reset, ap and sp) 6 - ns t hd;dat input data hold time (any pin except scl, sda, reset, ap and sp) 3 - ns
1997 jan 06 24 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 notes 1. at maximum supply voltage with highly active input signals. 2. the data is for both input and output direction. 3. with llc in input mode. in output mode, with a crystal connected to xtalo/xtali duty factor is typically 50%. 4. if an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 5. for full digital range, without load, v dda = 3.3 v. the typical voltage swing is 1.35 v, the typical minimum output voltage (digital zero at dac) is 0.2 v. crystal oscillator f n nominal frequency (usually 27 mhz) 3 rd harmonic - 30 mhz d f/f n permissible deviation of nominal frequency note 4 - 50 10 - 6 +50 10 - 6 c rystal specification t amb operating ambient temperature 0 70 c c l load capacitance 8 - pf r s series resistance - 80 w c 1 motional capacitance (typical) 1.5 - 20% 1.5 + 20% ff c 0 parallel capacitance (typical) 3.5 - 20% 3.5 + 20% pf data and reference signal output timing c l output load capacitance 7.5 40 pf t h output hold time 4 - ns t d output delay time - 25 ns c, y and cvbs outputs v o(p-p) output signal voltage (peak-to-peak value) note 5 1.20 1.45 v r int internal serial resistance 1 3 w r l output load resistance 75 300 w b - 3db output signal bandwidth of dacs 10 - mhz ile lf integral linearity error of dacs - 3 lsb dle lf differential linearity error of dacs - 1 lsb symbol parameter conditions min. max. unit
1997 jan 06 25 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 handbook, full pagewidth mbe742 llc clock output 0.6 v 1.5 v 2.6 v 2.0 v 0.8 v 2.4 v 0.6 v input data output data not valid valid valid not valid valid valid llc clock input 0.8 v 1.5 v 2.4 v t high t hd; dat t llc t high t llc t d t hd; dat t hd; dat t su; dat t f t f t r t r fig.8 clock data timing. the data demultiplexing phase is coupled to the internal horizontal phase. the phase of the rcv2 signal is programmed to tbf (tbf for 50 hz) in this example in output mode (rcv2s). handbook, full pagewidth mp(n) llc cb(0) y(0) cr(0) y(1) cb(2) rcv2 mgb699 fig.9 functional timing.
1997 jan 06 26 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 fig.10 rtci timing. handbook, full pagewidth 128 13 14 19 67 69 72 74 68 01 0 0 21 rtci hpll increment fscpll increment (1) h/l transition count start 4 bits reserved (7) valid sample invalid sample not used in saa7120/21 5 bits reserved (7) 8/llc mbh789 low time slot: (2) (3) (5) (6) (4) (3) reset bit: only from saa7111 decoder. (4) fise bit: 0 = 50 hz, 1 = 60 hz. (5) odd/even bit: odd/even from external. (6) colour detection: 0 = no colour detected, 1 = colour detected. (7) reserved bits: 232 with 50 hz systems, 229 with 60 hz systems. (1) saa7111 provides (22:0) bits, resulting in 3 reserved bits before sequence bit. (2) sequence bit pal: 0 = (r - y) line normal, 1 = (r - y) line inverted ntsc: 0 = no change. explanation of rtci data bits 1. the condenc generates the subcarrier frequency out of the fscpll increment if enabled (see item 6.). 2. the pal bit indicates the line with inverted r - y component of colour difference signal. 3. if the reset bit is enabled (rtce = 1; decph = 1; phres = 00), the phase of the subcarrier is reset in each line whenever the reset bit of rtci input is set to 1. 4. if the fise bit is enabled (rtce = 1; decfis = 1), the condenc takes this bit instead of the fise bit in subaddress 61h. 5. if the odd/even bit is enabled (rtce = 1; decoe = 1), the condenc ignores its internally generated odd/even flag and takes the odd/even bit from rtci input. 6. if the colour detection bit is enabled (rtce = 1; deccol = 1) and no colour was detected (colour detection bit = 0), the subcarrier frequency is generated by the condenc. in the other case (colour detection bit = 1) the subcarrier frequency is evaluated out of fscpll increment. if the colour detection bit is disabled (rtce = 1; deccol = 0), the subcarrier frequency is evaluated out of fscpll increment, independent of the colour detection bit of rtci input.
1997 jan 06 27 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 application information handbook, full pagewidth 2 w (1) 4.7 w 75 w agnd 30 cvbs dac1 dac2 dac3 v dda3 u cvbs 1.23 v (p-p) (2) 10 w 75 w agnd y u y 1.00 v (p-p) (2) mbh786 10 w 75 w agnd agnd dgnd c u c 0.62 v (p-p) (2) 31 agnd agnd v dda2 28 32, 33 5, 18, 38 v dda1 + 3.3 v analog supply + 3.3 v digital supply v ssd1 , v ssd2 , v ssd3 v ddd1 , v ddd2 , v ddd3 v ssa1 , v ssa2 25 36 6, 17, 39 35 34 xtali xtalo 10 pf 10 pf x1 (3) use one capacitor for each v ddd 2 w (1) 27 v dda4 2 w (1) 24 0.1 m f 0.1 m f agnd 0.1 m f agnd 0.1 m f dgnd dgnd 0.1 m f 0.1 m h 1 nf 3rd harmonic 27.0 mhz digital inputs and outputs saa7120/21 fig.11 application environment of condenc. (1) typical value. (2) for 100/100 colour bar. (3) order no. 4312 065 02341.
1997 jan 06 28 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 0.85 0.75 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 92-11-17 95-02-04 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p q detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1997 jan 06 29 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 jan 06 30 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 jan 06 31 philips semiconductors preliminary speci?cation digital video encoder (condenc) saa7120; saa7121 notes
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go to philips semiconductors' home page select & go... start part catalog & datasheets catalog by function discrete semiconductors audio clocks and watches data communications microcontrollers peripherals standard analog video wired communications wireless communications catalog by system automotive consumer multimedia systems communications pc/pc-peripherals cross reference models packages application notes selection guides other technical documentation end of life information datahandbook system relevant links about catalog tree about search about this site subscribe to enews catalog & datasheets search saa7120; saa7121 saa7120; saa7121 information as of 2000 - 08 - 25 saa7120; saa7121; digital video encoder (condenc) the saa7120; saa7121 encodes digital yuv video data to an ntsc or pal cvbs or s-video signal. the circuit accepts ccir compatible yuv data with 720 active pixels per line in 4 :2 :2multiplexed formats, for example mpeg decoded data. it includes a sync/clock generator and on-chip dacs. l monolithic cmos 3.3 v (5 v) device l digital pal/ntsc encoder l system pixel frequency 13.5 mhz l accepts mpeg decoded data on 8-bit wide input port; input data format cb-y-cr (ccir 656), sav and eav l three dacs for y, c and cvbs, two times oversampled with 10 bit resolution l real time control of subcarrier l cross colour reduction filter l closed captioning encoding and wst- and nabts-teletext encoding including sequencer and filter l line 23 wide screen signalling encoding l fast i 2 c-bus control port (400 khz) l encoder can be master or slave l programmable horizontal and vertical input synchronization phase l programmable horizontal sync output phase l internal colour bar generator (cbg) l 2 x 2 bytes in lines 20 (ntsc) for copy guard management system can be loaded via i 2 c-bus l down-mode of dacs l controlled rise/fall times of synchronization and blanking output signals ? description ? features ? datasheet ? blockdiagram ? products, packages, availability and ordering ? find similar products to be kept informed on saa7120; saa7121, subscribe to enews. subscribe to enews description features
l macrovision pay-per-view copy protection system rev.7 and rev.6.1 as option. this applies to saa7120 only. the device is protected by usa patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. use of the macrovision anti-copy process in the device is licensed for non-commercial home use only. reverse engineering or disassembly is prohibited. please contact your nearest philips semiconductors sales office for more information. l qfp44 package. saa7120; saa7121 links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. the similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category. datasheet type nr. title publication release date datasheet status page count file size (kb) datasheet saa7120; saa7121 digital video encoder (condenc) 06-jan-97 preliminary specification 32 225 download blockdiagram blockdiagram of saa7120h products, packages, availability and ordering partnumber north american partnumber order code (12nc) marking/packing package device status buy online saa7120h/01 9352 434 50551 standard marking * tray dry pack, bakeable, single sot307 full production - saa7120hb 9352 434 50557 standard marking * tray dry pack, bakeable, multiple sot307 full production - saa7121h/01 SAA7121HB - s 9352 434 60551 standard marking * tray dry pack, bakeable, single sot307 full production - SAA7121HB 9352 434 60557 standard marking * tray dry pack, bakeable, multiple sot307 full production - find similar products:
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